The present invention relates generally to differential comparators, and more specifically to offset correction within differential comparators.
A difference comparator is a circuit that accepts inputs and determines a difference between them. Typical difference comparators take two inputs and return a signal indicating which of the signals is higher. Many circuits use difference comparators, such as an analog to digital converter (ADC). As integrated circuit designs continue to decrease in size, and power requirements continue to be lowered, characteristics that were not once very important in circuit design have come to the forefront. For example, given the close placement of components on typical integrated circuit chips, parasitic charges and the like have become important factors that must be dealt with in the design of circuits.
Further, difference comparators are increasingly called on to make discrimination of differences in ever faster and faster times. For example, in communications circuits, strict tolerances on difference comparators have rendered some previous designs unsuitable for use, since they cannot accurately provide a quick enough difference comparison, or cannot work within the tolerances required by modern circuitry.
In communications networks such as 1000BaseT communications chips, for example, a difference comparator must at least be able to presently provide a decision time of less than about 3 nanoseconds, and must be able to accommodate 50 millivolts (mV) of difference between a reference common mode and a signal common mode to be applicable to the present type of application.
FIG. 1 shows a difference comparator comprising two input sources hooked to two current sources. The current for each source splits based on the voltages on the input gates. If Vin and Vref have the same common mode voltage, the current in the top diode devices is the same as a differential voltage. If, however, the common modes of the signals are not the same, non-linearities in the devices hurt performance. Any significant amount of signal swing reduces performance greatly.
FIG. 2 shows a difference comparator with input signals split so that positive signals are presented to a first differential pair, and negative signals are presented to another differential pair. The currents are subtracted from a constant current source on the right side, which helps to eliminate the swing problem of the device of FIG. 1, but which requires very sensitive matching of devices between the top and the bottom. In fact, it is not currently possible to easily match devices sufficiently closely to allow for reasonable operation of the device of FIG. 2. Temperature and process variations affect this circuit too much for it to be reliable. A skew in the P vs N parameters for the two differential pairs causes a mismatch in the output currents resulting in no rejection of the common mode difference
Therefore, what is needed is a difference comparator capable of good common mode rejection, which corrects offset, and which operates at high speed.
In one embodiment, a differential comparator comprises an input stage, and an operational amplifier comprising a differential current mirror circuit to provide differential output currents. The output currents are established in response to input signals, a common mode signal, and offset signals.
In another embodiment, an analog to digital converter (ADC) comprises a difference comparator and a latch connected to an output of the difference comparator. The difference comparator comprises a capacitively coupled input stage, and an operational amplifier comprising a differential current mirror circuit to provide differential output currents. The output currents are established in response to input signals, a common mode signal, and offset signals.
An operational amplifier, in another embodiment, comprises a main current control branch comprising a first differential pair of transistors. Each of the pair of first differential transistors are coupled in series with a diode connected transistor. The gates of the first differential pair are connectable to receive input voltages. An output branch comprises a pair of current mirror transistors each gate connected to a gate of one of the diode-connected transistors. A gain branch comprises a second differential pair of transistors. Each of the pair of second differential transistors are connected to a drain of one of the current mirror transistors and gate connected to one of the input voltages. A zeroing branch comprises a tail current transistor having its drain coupled to ground, and a third differential pair of transistors each connected between a gate of one of the diode connected transistors and the tail current transistor. Each transistor of the third differential pair has a gate connected to a common mode reference voltage. A fourth differential pair of transistors are each connected between a drain of one of the current mirror transistors and gate connected to one of a positive and a negative offset input.
Other embodiments are described and claimed.